SUBDESIGN ggtv2 ( red_out[3..0] : OUTPUT; -- red video output green_out[3..0] : OUTPUT; -- green video output blue_out[3..0] : OUTPUT; -- blue video output d[3..0] : INPUT; -- multiplexed data input csync, hsync : INPUT; pix_clk : INPUT; -- 32Mhz master clock sc_out : OUTPUT; -- Subcarrier output for video enc. Generated by dividing -- pix_clk by 9. csync_out : OUTPUT; -- buffered composite sync output /oe : INPUT ; -- /OE, when low enable outputs vcc5 : OUTPUT; -- inverse of /OE, to switch off +5v rail --hout : OUTPUT; -- for measuring hsync propagation delay pix_clk_out : OUTPUT; d3_out : OUTPUT; ) VARIABLE ffa, ffb, ffc : DFF; red_dff[3..0] : DFF; green_dff[3..0] : DFF; blue_dff[3..0] : DFF; red_dff_align[3..0] : dff; green_dff_align[3..0] : dff; div_nine[3..0] : DFFE; red_tri[3..0] : TRI; green_tri[3..0] : TRI; blue_tri[3..0] : TRI; csync_tri : TRI; sc_tri : TRI; BEGIN ffa.d = !ffc.q; ffb.d = ffa.q; ffc.d = ffb.q; ffa.clk = pix_clk; ffb.clk = pix_clk; ffc.clk = pix_clk; ffa.clrn = !hsync; ffb.clrn = !hsync; ffc.clrn = !hsync; red_dff[].clk = ffa.q; red_dff_align[].clk = !ffb.q; green_dff[].clk = ffc.q; green_dff_align[].clk = !ffb.q; blue_dff[].clk = !ffb.q; --blue_dff_align[].clk = ffc.q; red_dff[].d = d[]; red_dff_align[].d = red_dff[].q; green_dff[].d = d[]; green_dff_align[].d = green_dff[].q; blue_dff[].d = d[]; div_nine[].ena = !/oe; div_nine[].clk = pix_clk; IF div_nine[] >= 8 THEN div_nine[] = 0; ELSE div_nine[].d = div_nine[].q + 1; END IF; IF div_nine[] >= 4 THEN sc_tri.in = vcc; ELSE sc_tri.in = gnd; END IF; sc_out = sc_tri.out; sc_tri.oe = !/oe; -- csync_out = csync; csync_tri.in = csync; csync_out = csync_tri.out; csync_tri.oe = !/oe; red_tri[].in = red_dff_align[].q; red_out[] = red_tri[].out; red_tri[].oe = !/oe; green_tri[].in = green_dff_align[].q; green_out[] = green_tri[].out; green_tri[].oe = !/oe; blue_tri[].in = blue_dff[].q; blue_out[] = blue_tri[].out; blue_tri[].oe = !/oe; vcc5 = !/oe; --hout = pix_clk; --pix1 = pix_clk; --pix2 = pix1; pix_clk_out = ffc.q; d3_out = d[3]; END;